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an - 1177 application note one technology way ? p. o . box 9106 ? norwood, ma 02062 - 9106, u.s.a. ? tel: 781.329.4700 ? fax: 781.461.3113 ? www.analog.com lvds and m- lvds circuit implementation guide by dr. conal watterson rev. 0 | page 1 of 12 introduction low voltage differential signaling (lvds) is a standard for communicating at high speed in point - to - point applications. multipoint lvds (m - lvds ) is a similar standard for multi - point applications. both lvds and m - lvds use differential signaling , a two - wire communication method where receivers detect data based on the voltage difference between two complementary electrical signals. this greatly improves noise immunity and minimizes emissions. lvds lvds is a lower power alternative to emitter - cou pled logic (ecl) or positive emitter - coupled logic (pecl). the primary standard for lvds is tia/eia - 644. an a lternative standard sometimes used for lvds is ieee 1596.3 sci, scalable coherent interface . lvds has been widely adopted for high - speed backplane, cabled , and board - to - board data transmission and clock distribution, a s well as communication links within a single pcb. advantage s of lvds include ? communication at speeds of up to 1 g bps or more ? reduced electromagnetic emissions ? increased immunity to nois e ? low power operation ? common - mode range allowing differences of up to 1 v in ground offset m- lvds t he standard tia/eia - 899 for multipoint low voltage differ - ential signaling (m - lvds ) e xtends lvds to address multipoint applications. m - lvds allows higher sp eed communication links than tia/eia - 485 (rs - 485) or controller area network (can ) with lower power. see the references section for a list of the standards referred to in this application note. additional f eatures of m- lvds over l vds include ? increased driver output strength ? controlled transition times ? extended common - mode range ? option of failsafe receivers for bus idle condition lvds/m - lvds application con siderations this application note considers the following aspects concerning lvds/m - lvds circuit implementation : ? bus types and topologies ? clock distribution applications ? characteristics of lvds/m - lvds signaling ? te rm inati on and pcb layout ? jitter and s kew ? data encoding and sy nchronization ? isolation why use lvds or m- lvds? lvds and m -l vds are compared to other multi point and point - to - point protocols in figure 1 . both standards have low power requirements. lvds and m - lvds are characterized by differential signaling with a low differential voltage swing. m - lvds specifies an increased differential output voltage compared to lvds in order to allow for the increased load from a multipoint bus. both protocols are designed for high - speed communication. typical applications utilize pcb traces or short wired/backplane l inks. the common mode range of lvds is designed for these applications. m- lvds has an extended common mode range compared to lvds to allow for the additional noise in a multipoint top olog y. long distances (>1km) typ. max. data rate: 16mbps rs-485 medium distances (max. 40m) robust protocol max. data rate: 1mbps can multipoint medium distances (max. 20m to 40m) low power, high speed typ. data rate: 100mbps, 200mbps m-lvds short distances (max. 5m to 10m) low power, high speed max. data rate: >1gbps lvds short distances high speed max. data rate: ~3gbps pecl point-to-point 11236-001 figure 1. comparison of communication s tandards
an-1177 application note rev. 0 | page 2 of 12 table of contents introduction ...................................................................................... 1 lvds/m - lvds application considerations ................................ 1 why u se lvds or m - lvds? ........................................................... 1 revision history ............................................................................... 2 bus types and topologies ............................................................... 3 point - to - point ............................................................................... 3 multi -d rop .................................................................................... 3 multipoint ...................................................................................... 3 clock distribution applications ..................................................... 4 multi -d rop clock distribution .................................................. 4 point - to - point clock distribution ............................................. 4 clock distribution using m - lvds ........................................... 4 differential signalling and lvds/m - lvds .................................. 5 definitions a nd output levels ....................................................5 receiver thresholds ......................................................................5 transmission distance ..................................................................6 termination and pcb layout ..........................................................7 controlled impedances ................................................................7 jitter, skew, data encoding, and synchronization ........................8 what is jitter? .................................................................................8 what is skew? ................................................................................8 data encoding and synchronization ..........................................9 isolation ........................................................................................... 10 references ........................................................................................ 11 related links ............................................................................... 11 rev ision history 3 /1 3 revision 0: initial version
application note an-1177 rev. 0 | page 3 of 12 bus types and topologies standard tia/eia - 644 lvds devices allow low power, high speed communication. the advantages of lvds can also be applied to multipoint applications by using tia/eia - 899 devices. bus topology is one of the main factors relat ing to which lvds or m - lvds devices are use d in an application. point - to - point point - to - point bus topologies consist of a single driver and single receiver connected together using one pair of wires or traces . figure 2 demonstrates a typical configuration, where the receiving end of the link has a termination resistor. this is the most common application for lvds devices. multiple pairs of wires or traces can be used to create additional ch annels of communication and increase total bandwidth between two points . 11236-002 d out? d out+ r in? r in+ d in r out r t lvds driver lvds receiver figure 2 . lvds point -to- point link analog devices , inc., has a portfolio of lvds drivers and receivers for one, two or four lvds channels as shown in table 1 . unused outputs should be left open circuit. table 1 . lvds d rivers and r eceivers part no. tx rx part no. tx rx adn4661 1 0 adn4665 4 0 adn4662 0 1 ADN4666 0 4 adn4663 2 0 adn4667 4 0 adn4664 0 2 adn4668 0 4 m- lvds can also be used in a point - to - point topology , where the same transceiver device is used for the driver circuit (with receiver disabled) and the receiving circuit (with driver disabled) . multi - drop a single driver can be connected to multiple receivers using a mu lti - drop bus topology as shown in figure 3 . lvds is designed for point - to - point applications and so in a multi - drop configuration, the number of receivers that can be connected and the signaling distance can be limited . m - lvds can be used in a multi - drop topology to drive up to 32 nodes across longer distances compared to lvds. d out? d out+ r in? r in+ d in r out r out r t lvds driver lvds receivers 11236-003 figure 3 . lvds multi- drop bus multi point in networks where multiple devices can either send or receive, a multipoint bus topology may be used. m - lvds is designed for such multi - point applications, allowing up to 32 nodes to be connected to a single bus. there are two types of multipoint buses, half - duplex and full duplex , shown in figure 4 and figure 5 , respectively. in a half - duplex bus, two wires are used such that one device may transmit, and the other devices can receive. in a full - duplex bus, four wires are used, allowing one node to concurrently transmit back to another trans mitting node (that is, slave devices responding as broadcast commands are sent by the master to all nodes). 11236-004 b a b a di ro di ro ro di r t r t mlvds transceivers figure 4. m- lvds half- duplex bus 11236-005 z y z y b a b a di ro di ro r t r t r t r t mlvds transceivers ro di ro di figure 5. m- lvds full - duplex bus another f actor to be conside red in multi point buses is the bus idle condition. when no device is transmitting, the differential voltage on a terminated bus will be close to 0 v. this means that for a standard receiver with symmetrical input thresholds, the receiver output will be und efined. this corresponds to the type 1 m - lvds receivers with an input threshold of 50 mv. in order to provide a guaranteed receiver output state (output low) in the bus idle condition , type 2 m - lvds receivers have an offset receiver input threshold of + 50 mv to +150 mv. table 2 . m - lvds t ransceivers part no. rx type duplex data rate adn4690e 1 half 100 adn469 1e 1 half 200 adn4692e 1 full 100 adn4693e 1 full 200 adn4694e 2 h alf 100 adn4695e 2 full 100 adn4696e 2 half 200 adn4697e 2 full 200
an-1177 application note rev. 0 | page 4 of 12 clock distribution applications differential signaling , such as lvds , is a good choice for distributing clock signals around a circuit board. in addition to the benefits of the common - mode noise immunity of lvds, a particular advantage for clock distri bution applications is that radiated emissions are reduced due to the coupling between the two opposing signals. multi - drop clock distribut ion in many applications, multiple nodes in a circuit may depend on a single clock source. a simple approach to distri buting a single clock source to multiple nodes using lvds, is to use a multi - drop bus topology as shown in figure 6 . the lvds outputs of a clock source are connected to a pair of signal traces that have short stubs to the various nodes relying on the clock. 11236-006 d out? d out+ r in? r in+ clk clk clk clk r t lvds clock source lvds clock inputs figure 6. multi -d rop lvds clock distribution the disadvantages of this approach are that the number of nodes that can be connected is limited and stubs contribute to degradation of the signal integrity ( that is, adding jitter). stub lengths and impedances must be carefully controlled. point - to - point clock distribu tion a single clock source can be connected to a single node requiring an lvds clock input using a point - to - point link. this can be extended to supply multiple nodes by means of an lvds buffer acting as a fan - out device . this separate component receives the lvds clock output from the clock source, and in turn provides this clock signal to multiple lvds drivers in the device to drive multiple p oint - to - point links to receiving nodes. the advantage of this approach is that timing on the clock signal can remain unaffected by stubs. an example of such a device is the adn4670 clock distribu tion buffer. this allows one of two clock sources to be distributed on up to 10 outputs as shown in figure 7 . the outputs can be enabled and disabled by means of a serially programmable register, which is also used to select the c lock source. 12-bit counter 11-bit shift register 11-bit control register 10 lvds point- to-point links q9 q8 q7 q6 q5 q4 q3 q2 q1 q0 ck si en clk0 clk1 mux mux 1 0 clk0 clk1 q9 q8 q7 q6 q5 q4 q3 q2 q1 q0 0 1 adn4670 node 9 clock source clock source node 0 11236-007 figure 7. adn4670 application distributing a clock source t o 10 n odes via point - to -point lvds connections any buffer adds a small amount of jitter when ins erted between the initial lvds output and the eventual lvds input, but the adn4670 has been designed to have low additive jitter of <300 f s. skew between the 10 outputs is kept to less than 30 p s with clock signals of up to 1.1 ghz. clock distribution using m-lvds another option for clock distribution is using m - lvds transceivers to distribute the clock to up to 32 nodes in a multi - drop (or multi point) topology. type 1 m - lvds rece ivers (such as in the adn4690e to adn4693e ) are suited to such applications because there is no offset in the receiver threshold (this offset can res ult in duty cycle distortion for a clock signal) . the adn4690e to adn4693e m- lvds transceivers with type 1 receivers also have addit ional slew- rate limit ing of the edges from the dr iver outputs , which further limits radiated emissions and the effect of reflections from stubs.
application note an-1177 rev. 0 | page 5 of 12 differential signalling and lvds/m -lvds differential transmission is communication where two complementary s ignals are transmitted, with the received signal comprising the difference between the two signal lines. this form of communication, used by both lvds and m - lvds , has two distinct advantages, high noise immunity and low emissions. the high noise immunity arises because typically a noise source couple s equally onto both signal lines, leaving the differential signal unaffected. emissions from differential signaling are low due to the tight coupling between the two complementary signal lines when using a typ ical medium (twisted pair cable, or closely placed strip line). definitions and o utput levels for lvds and m- lvds, one signal line is non inverting ( that is, high for a logic 1 and low for a l ogic 0) and the othe r signal line is inverting (that is, the comp lement of the non inverting signal). the difference in voltage between the two signal lines is termed the differential voltage, v od . v od is also shorthand for the magnitude of the differential voltage (positive or negative), or |v od |. the two signal lines each have a maximum voltage swing of |v od |, centered on the common - mode voltage, v oc (also referred to as the offset voltage, v os ). the differential voltage swings around 0 v. typical lvds signal levels are shown in figure 8 , toge ther with the differential signal v od and common - mode voltage v oc . i n this figure, v out+ is the non inverting signal and v out ? is the inverting signal. 11236-008 v out+ v out? 1.35v v oc = 1.2v 1.05v 0v logic 0 logic 1 logic 1 0.3v ?0.3v v od (v out+ ? v out? ) |v od | |v od | figure 8 . lvds output levels the differential voltage on an lvds or m - lvds bus is generated by a driver current source. non inverting lvds driver outputs or receiver inputs are generally denoted with a + and inverting driver outputs or receiver inputs with a ?. pin names are shown for the adn4663 2- channel lvds driver and adn4664 2- ch annel lvds receiver in figure 9 . m - lvds follows the convention of rs - 485 physical layer transceivers in nam ing the bus lines a for the noninverting signal and b for the inverting signal, or y and z for driver outputs on a full - dup lex transceiver. 11236-009 d in1 d out1+ d out1? v cc adn4663 d in2 d out2+ d out2? gnd r out1 r in1+ 100? 100? r in1? v cc adn4664 gnd r out2 r in2+ r in2? figure 9. adn4663 and adn4664 2-c hannel lvds p oint -to- point the distinction between lvds a nd m - lvds and other differential signaling standards is that they have a low output swing. t he differential output voltage and common mode range specifications of lvds and m - lvds are shown in figure 10 . for lvds, the output voltag e swing , |v od |, is a minimum of 250 mv and a maximu m of 450 mv with a load of 100 ? . this allows low power operation and ensure s that while transitions are fast, to allow high data rates, the reduced output swing mean s that the slew rate is not too severe. rise and fall times are generally in the region of hundreds of picoseconds , resulting in slew rates of around 0.5 v/ns to 2.5 v/ns . 11236-010 250mv 450mv 480mv 650mv m-lvds lvds min v od min v od max v od max v od 0v to 2.4v ?1v to 3.4v 4v 3v 2v 1v 0v ?1v m-lvds lvds common-mode voltage differential output voltage figure 10 . lvds and m - lvds signaling levels m- lvds has slew - rate limited drivers to enhance the robustness of the signaling when there are additional im pedance discontinuities from multiple drivers/receivers and stubs. this mean s that m - lvds is limited to lower data rates compared to lvds. t he adn4690e through adn4697e are available with options for 100 mbps or higher speed 200 mbps. another characteristic of m - lvds is increased driver strength, resulting in a minimum output voltage swing |v od | of 480 mv and a maximum of 65 0 mv with a load of 50 ? (two termination resistors of 100 ?, one either end of the bus). receiver thresholds the receiver thresholds are the differential voltage levels above or below which the r eceived signal is considered a logic 1 or a l ogic 0. for lvds, a posit ive v od >= +100 mv corresponds to a l ogic 1 and a negative v od <= - 100 mv corresponds to a l ogic 0.
an-1177 application note rev. 0 | page 6 of 12 for type 1 m - lvds receivers, a positive v od +50 mv corresponds to a l ogic 1 and a negative v od ? 50 mv corresponds to a l ogic 0. in between these volt age thresholds is the transition region . if an input signal remains at a voltage level between the thresholds, the receiver output is undefined under lvds ; it can be high or low. this can occur if no active lvds driver is connected to the receiver, or if there is a short circuit. analog devices lvds receivers incorporate a failsafe feature, so that in these cases, the receiver output is high. 11236-011 differential input voltage (v ia ? v ib ) [v] logic 1 logic 0 undefined m-lvds type 1 receiver output logic 1 logic 0 undefined logic 1 logic 0 lvds receiver output *logic 1 for lvds receivers with failsafe m-lvds type 2 receiver output 0.15 0.05 0.10 0 ?0.05 ?0.10 ?0.15 0.15 0.05 0.10 0 ?0.05 ?0.10 ?0.15 undefined* figure 11 . receiver thresholds for lvds and m - lvds with m - lvds, any node on the bus can transmit, but when no node is active , all driver outputs are disabled. as with lvds, this results in a differential output voltage in the undefined region for type 1 receivers. in order to provide a failsafe condition, m - lvds defines type 2 receivers tha t have an offset receiver threshold of >= +150 mv for a logic high and <= +50 mv for a logic low. this means that the failsafe output from type 2 m - lvds receivers is a logic low. receiver thresholds are shown in figure 11 for lv ds receivers, m - lvds type 1 receivers and m - lvds type 2 receivers. transmission distanc e both lvds and m - lvds transmission distances are affected by two main factors: the transmission medium and the data rate. the standard deciding factor of whether a give n transmission distance is practical, is how much jitter is observed by recei ving nodes. this is application de pendent; some applications require 5% or less jitter, whereas others tolera te up to 20%. pcb traces typically allow transmission dista nces on the order of ten s of centimeters , whereas twisted pair cable allows transmission on the order of meters for lvds or tens of meters for m - lvds. different specifications of pcb c onstruction or cable types affect the signal differently and thus have an impact on the maximum transmission distance. higher data rates greatly cons train the transmission distance; lvds at 1 gbps might only be transmitted across high - quality cables of 1 meter (possibly with additional signal conditioning) , but at 100 mbps may be transmi tted across 10 meters (depending on the cable type ). m - lvds can generally be transmitted across longer cables due to the increased driver strength, but data rates of hundreds of mbps require shorter cables than data rates of only ten s of mbps. figure 12 provides a general indication of the combinations of lvds and m - lvds data rates and cable lengths typical for some applications. 1200 0 200 400 600 800 1000 0 25 20 15 10 5 11236-012 data rate (mbps) cable length (m) lvds m-lvds figure 12 . cable length (twisted - pair ) vs. data rate for som e typical lvds and m - lvds a pplications other factors influencing the maximum distance include: ? the transmitter specifications . ? other transmission medium components , such as vias (on pcb traces) or connectors for cables. ? for m - lvds or multi - drop lvds, the nu mber of nodes on the bus and the stub lengths. tia/eia - 644 (lvds) and tia/eia - 899 (m - lvds) recommend testing intended cable lengths in the application if possible, due to the multiple factors involved that affect the possible cable length. this allows the jitter on the received signal to be measured, providing a guide as to how practical a given cable type and length is. measurements can be taken using an eye diagram ; the adn4696e driver output is shown in figure 13 . 11236-013 1ns/div 200mv/div figure 13 . adn4696e driver output eye diagram
application note an-1177 rev. 0 | page 7 of 12 termination and pcb layout high speed communication links , such as those used for lvds and m - lvds , should be considered in the context of trans - mission line theory, whether cables or pcb traces are used. the high data rates of lvds and m - lvds require fast rise times, meaning that i mpedance discontinuities and the end of the com munication link can significantly affect the transmitted signal as it propagates from the driver to the far ends of the bus. to avoid degradation of the signal, controlled impedances along the communication medium, as well as proper termination, are requir ed. d? d+ r? z 0 z 0 r+ tx rx r t driver z 0 = r t (termination matches cable/track impedance) receiver 11236-014 figure 14 . point -to- point termination the termination resistor should match the impeda nce of the communication medium; for lvds, this is usually 100 ?. for a simple point - to - point link, it is only necessary to terminate the e nd of the bus furthest from the driver , as shown in figure 14. for multi - drop buses, the same termination can be used if the driver is at one end of the bus. otherwise, both ends of the bus need to be terminated. with m - lvds, both ends of the bus are terminated, and the drivers are designed with increased drive strength , partly to accommodate the double termination (the effective load is 50 ? rather than 100 ?) . some devices have built - in termination. this termination may need to be disabled if the device is located at the wrong point on the bus for termination, or if there is already proper termination on the bus. if there are two or mor e 100 ? resistors for lvds, or more than two for m - lvds , then the bu s is over - terminated. this result s in reduced signal amplitude and increased reflections, combining to decrease noise immunity, degrade timing accuracy and reducing the maximum transmissio n distance. controlled impedance s one difficulty in lvds and m - lvds links is providing a consistent controlled impedance across the bus. for links across a single pcb, impedance discontinuities can easily arise from vias, mismatches in trace lengths betwee n each signal in a differential pair, and changes in the spacing between tracks, or the size of tracks. for differential signaling on a pcb, the two signal traces are usually placed close together and tightly coupled. this means that the signals have a common field, cancelling emissions and reducing susceptibility to common - mode noise. one difficulty that arises is that if the traces need to move apart, for example, to reach a connector, then a change in impedance between the signals is introduced. it can b e preferable to relax how closely the signals are coupled , but maintain consistent spacing and track thickness across the entire link. sharp turns or a series of bends in the pcb traces can also affect the signal quality. generally, turns in the pcb traces should be minimized and kept to 45- degree angles (ideally with curves rather than sharp angles). skew can be introduced between the two signals in a differential pair if one signal follows a longer trace than the other does . it may not always be possible to have traces exactly the same length, but pcb layout should attempt to keep the trace lengths matched. connectors should be chosen to minimize any difference in impeda nce that they present on a bus, and cables or backplanes should also match the impedanc e of pcb traces where possible . backplane connections can add significant capacitance to the bus and it may be necessary to reduce the data rate or pcb trace distances to allow for any degradation of the data signal that occurs. 1 1236-015 figure 15 . eval - adn469xefdebz customer evaluation board an example high speed pcb layout for m - lvds is shown in figure 15 , the eval - adn469xefdebz evaluation board for full - duplex adn469xe family m - lvds transceivers. track leng ths on a, b, y , and z are matched and have a 50 ? impedance created using a 4 - layer board layout. the termination resistor placem ent is next to the device pins. the circuit does not fully correspond to an application layout because there are additional com ponents , such as test points and jumper options.
an-1177 application note rev. 0 | page 8 of 12 jitter , skew , data encoding , and synchronization with high speed differential signaling , such as lvds and m- lvds, accurate timing is critical to the performance of a system. pcb traces, connectors , and c abling can degrade the performance of data and clock signa ls, requiring that a margin for error is also present in system timing. this means that careful timing analysis may be required to achieve the maxi - mum throughput on an lvds or m - lvds communication link. modern fpgas and processors also have built - in capabilities to correct for timing errors, although there may be clearly defined limits to the amount of jitter tolerated, for example. what is jitter? jitter refers to the apparent movement of a signal edge with respect to the ideal time position of that signal edge. if a periodic signal is observed on an oscilloscope, the edges literally jitter back and forth with respect to the reference point. 11236-016 tie eye jitter (peak- to-peak) ideal actual (one pass) actual (multiple passes) figure 16 . waveforms showing time interval error, jitter and eye jitter can be quantified simply as time interval error , the time difference between when a signal edge occurs, and when it should occur. usually in order to determine the sources of jitter, a large number of tie samples are recorded to build a histogram, from which deterministic jitter can be separated from random jitter. tota l jitter can be quantified as a peak - to - peak value when bounded to a specific quantity of samples. the peak - to - peak value means the time difference between the earliest and latest edge observed during sampling. peak - to - peak jitter can be seen visually if multiple waveform samples are overlaid on an oscilloscope display (infinite persistence) , as shown in figure 16 . the width of the overlaid transitions is the peak - to - peak jitter, with the clear area in - between referred to as the eye . this eye is the area available for sampling by a receiver. random jitter occurs due to noise, both electrical and thermal. the result is a gaussian distribution to the time error , with this error introduced as random jitter. the jitter is unbounded ; when more samples are recorded, the probability function continues to grow. deterministic jitter is , by contrast, bounded. there is a fixed amount of this jitter in the system due to specific factors , such as the board layout and driver performance. periodic jitter is one type of deterministic jitter and refers to the time difference between each cycle compared to the ideal. period ic jitter is also record ed as a peak - to - peak value, that is, the difference between the longest and shortest periods observed what is skew? there are different definitions for skew, several of which are typical ly considered in designing high speed lvds links. the most basic de finition of skew is the difference in propagation time between the two signals in a differential pair. this means that edge transitions on one signal in a pair will not match up exactly with transitions on the complementary signal (the crossover will be as ymmetric). input actual output ideal output t plh = t phl t plh t phl pulse skew ( t phl ? t plh ) d? d+ d? d+ d? d+ 11236-017 figure 17 . waveforms illustrating pulse skew calculation pulse s kew on a differential signal refers to the difference between the low - to - high transition time (t plh ) and the high - to - low transition time (t phl ). this resu lt s in duty cycle distortion, that is, the bit period is longer or shorter for a l ogic 1 or logic 0. pulse skew is illustrated in figure 17. t he blue waveform correspond s to an input signal, the green waveform to an ideal output ( where propagation times on high - to - low and low - to - high transitions are matched) , and the red waveform to an actual output, where the difference between t plh and t phl results in pulse skew. channel - to - channel skew and part - to - part skew are s ome of the most important parameters in typical lvds applications because they have multiple data channels that need to remain synchronized . channel - to - channel skew refers to the difference, across all channels in a part, between the fastest and slowest low - to - high trans ition, or the fastest and slowest high - to - low transition (whichever is larger). part - to - part skew extends this concept to channels across multiple parts. skew across multiple channels (on one or multiple parts) is illustrated in figure 18 . the blue waveform corresponds to an input signal, with the four red waveforms comprising output channels on one or more parts. the difference between the fastest and slowest t plh is calculated, along with the difference between the fastest and sl owest t phl . the channel - to - channel or
application note an-1177 rev. 0 | page 9 of 12 part - to - part skew is the greater of these differences (in the case of figure 18 , the difference between the fastest and slowest t phl ). 11236-018 input actual output actual output (2nd) actual output (3rd) actual output (4th) t plh(fast) t phl(fast) t phl(slow) t plh(slow) t plh(slow) ? t plh(fast) t phl(slow) ? t phl(fast) channel-to-channel or part-to-part skew ( t phl(slow) ? t phl(fast) > t plh(slow) ? t plh(fast) ) d? d+ d? d+ d? d+ d? d+ d? d+ figure 18 . waveforms illustrat ing channel -to- channel or p art - to - part skew both channel - to - channel skew and part - to - part skew result in parallel data channels received out of phase relative to each other, even if they were synchronized at the transmitting end. this can caus e difficultie s in sampling across multiple channels. data encoding and synchroniz ation the challenges for lvds tim ing stem not only from the high speed transmission, but also from the data encoding. in many lvds applications, in order to increase bandwidth, multiple parallel lvds channels are used to transmit data. the transmitter must synchronize data transmitted on these channels and the receiver needs to sample each channel at the appropriate point so that data can be received at the same time across channels. in lvds applications using few channels, serial data is typically transmitted and at higher speeds. the high speed requires the recei ving device to synchronize quickly with the incoming data stream, and , in addition to accurately sampling each bit, the receiv ing device needs to detect frames of data in the incoming bit stream. to help the receiving device synchronize with the received data, a clock may be transmitted with the data channels. this is described as source - synchronous data transmission. there are s everal methods of transmitting the clock with the data. the clock may be transmitted as a parallel channel, with the clock period corresponding to one data bit (single data rate, sdr) or two data bits (double data rate, ddr). for serial lvds transmission, a frame clock may also be transmitted. an example of adc source - synchronous lvds outputs for sdr and ddr is shown in figure 19 . sample n sample n + 2 sample n + 1 clk+ sample n ? 7 bit 0 (lsb) bit 0 (lsb) bit 5 bit 0 (lsb) bit 5 bit 9 (msb) bit 4 bit 9 (msb) bit 4 sample n ? 7 sample n ? 6 bit 0 (lsb) clk? dco+ dco? d0+ d0? sample n ? 7 bit 9 (msb) sample n ? 6 bit 9 (msb) d9+ d9? analog input internal clock: lvds outputs: sdr (10 chs) ddr (5 chs) d0/d5+ d0/d5? d4/d9+ d4/d9? sample n ? 6 11236-019 figure 19 . adc input and source -synchronous lvds output waveforms an alter nati ve to dedicated clock channels is to embed the clock with the data. with the embedded clock method, fixed bits are inserted into the data stream, allowing a receiving node to detect these bits and synchronize with the incoming data. channel - to - channel and part - to - part skew can be compensated for when received by modern fpgas, using a scheme termed dynamic phase adjustment (dpa). the fpga generate s multiple phases of the received source - synchronous clock and match es each data channel to the best clock ph ase for sampling. if dpa is not available, then a strict timing budget must be adhered to. there must be a time interval remaining after transmitter channel - to - channel skew and the sampling time are subtracted from the bit period. this interval is termed the receiver skew margin. the transmitter channel - to - channel skew includes the skew across channels due to the transmitting node, the skew due to the medium and the clock skew relative to the data.
an-1177 application note rev. 0 | page 10 of 12 isolation external interfaces can be isolated from logi c circuits to prevent unwanted current flow that may damage or degrade the operation of electronic components. galvanic isolation, shown in figure 20 , allows information flow , but prevents current flow. complete isolation of data signals and power is possible using i coupler? digital isolation and iso power? power isolation . 11236-020 isolator point a point b isolation barrier information flow no current flow protect humans/ equipment eliminate grounding problems improve system performance figure 20 . galvanic isolation allows information flow while preventing ground current flow applications of isolation for lvds and m - lvds are safety isolation and/or functional isolation of board - to - board, back - plane, and pcb communication links. an example of safety i solation is a system with an m - lvds backplane where one or more plug - in cards are at risk from high voltage transients. isolating the m - lvds interface ensures that such fault conditions do not affect other circuits in the system. an example of an application where functional isolation is beneficial is measurement equipment. isolating lvds links, for example, between an adc and fpga, can provide a floating ground plane to boost the integrity of measurement data, minimizing interference from the rest of the application. the circuit shown in figure 21 is an isolated lvds i nterface circuit from the lab (cftl), demonstrat ing complete isolation of an lvds interface (see the references section) . the adum3442 provides digital isolation of the logic inputs to the adn4663 lvds driver and the logic outputs from the adn4664 lvds receiver. together with provision of isolated power using the adum5000 , a number of challenges to isolating lvds links in industrial and instrumentation applications are met that include the following: ? isolation of the logic signals to/from the lvds drivers/ receivers , ensuring standard lvds communication on the bus side of the circuit. ? highly integrated isolation using just two additional wide - body soic devices, the adum3442 and adum5000 , to isolate the standard lvds devices, the adn4663 and adn4664 . ? low power consumption com pared to traditi onal isolation (opto - couplers). ? multiple channels of isolation. this circuit demonstrates quad - channel isolation (in this case, two transmit and two receive channels). ? high speed operation; the isolation can operate at up to 150 mbps, facil itating basic lvds speed requirements. the circuit shown in figure 21 isolates a dual - channel lvds line driver and a dual - channel lvds receiver. this allows demonstration of two complete transmit and receive paths on a single boar d. osc rec v iso v dd1 v dd1 v dd2 reg adum5000 3.3v adum3442 iso 3.3v iso 3.3v d in1 d out1+ d out1 v cc adn4663 d in2 d out2+ d out2 lvds bus adn4664 r out1 r in1+ r in1 v cc r out2 r in2+ r in2 iso 3.3v fpga isolation barrier gnd in1 in2 out1 out2 r1 r2 11236-021 figure 21 . isolated lvds interface circuit (simplified schematic, all connections not shown)
application note an-1177 rev. 0 | page 11 of 12 references chen, boaxing. 20 06. i coupler? products with isopower? techn ology: signal and power transfer across isolation barrier using micro - transformers , technical article , (analog devices ). ieee standard 1596.3 - 1996, ieee standard for low - voltage differential signals (lvds) for scalable coherent interface (sci). marais, hein. 2009. rs- 485/rs - 422 circuit implementation guide , application note an - 960, analog devices, inc . tia/eia - 485- a standard, electrical characteristics of generators and receivers for use in balanc ed digital multipoint systems. tia/eia - 644 standard, electrical characteristics of low voltage differential signaling (lvds) interface circuits. tia/eia - 899 standard, electrical characteristics of multipoint - low - voltage differential signaling (m - lvds) interface circuits fo r multipoint data interchange. watte rs on, conal. 2012. controller area network (can) implementatio n guide, application note an - 1123 , analog devices, inc . watte rs on, conal. 2012. circuit note cn - 0256 , isolated lvds interface c ircuit, (analog devi ces, inc. related links resource description lvds/m - lvds we b page links to product pages and resources for lvds drivers, lvds receivers and m - lvds transceivers m - lvds web page introduction to and resources for the adn4690e to adn4697 e family of m - lvds transceivers cn - 0256 circuit note for isolated lvds interface circuit an - 960 application note for rs - 485/rs - 422 circuit implementation guide
an-1177 application note rev. 0 | page 12 of 12 notes ? 2013 analog devices, inc. all rights reserved. trademarks and regis tered trademarks are the property of their respective owners. an11236 -0- 3/13(0)

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